In recent years, with increases in integration density and performance of a semiconductor integrated circuit (LSI), a new micro fabrication technique has been developed. In particular, in order to speed up LSI, there has been more progress recently in changing wire materials from aluminum (Al) alloy, which has been used, to copper (Cu) or Cu alloy (i.e. Cu-containing material, collectively referred to as Cu hereinafter) having a low resistance. Micro fabrication of Cu by a dry etching process such as a reactive ion etching (RIE) that has been frequently used in formation of Al alloy wires is difficult. Therefore, a so-called damascene process, in which a Cu film is deposited on a grooved dielectric film, and the Cu film except for portions embedded in grooves is removed by chemical-mechanical polishing (CMP) method to form buried wires, is mainly used. In formation of Cu wires, grooves are formed on a dielectric film and then a titanium (Ti) film, as an example, is formed as a base metal film (barrier metal film) for preventing diffusion of Cu. It is common that a thin Cu seed film is thereafter formed on the surface by a sputter process and the like, and a laminated film having about hundreds of nanometers is formed by an electroplating process. Further, when multilayered Cu wires are formed, a wire forming method called dual damascene structure may be used. With this method, a dielectric film is deposited on lower layer wires, predetermined via holes (holes) and trenches for upper layer wires (wiring grooves) are formed, and then a barrier metal film and a Cu seed film are formed. Thereafter, Cu as a wire material is buried in the via holes and the trenches at the same time, and unwanted Cu on the upper layer is removed by CMP to planarize, whereby buried wires are formed.
With electroplating process, Cu is selectively grown from the surface of a Cu seed film on a groove bottom (bottom-up growth) to bury Cu in wiring grooves without void, whereby Cu wires are formed. However, when the aspect ratio of grooves increases, it becomes difficult to form the Cu seed film on the side wall of the groove with a sufficient amount. This causes so-called film breakage of the Cu seed film. At the film breakage portions, Ti as the base metal film is exposed to the surface. At portions where Ti is exposed to the surface, Ti oxide is easily formed, and a Cu film cannot be formed on the Ti oxide since Cu growth is difficult on the Ti oxide by the plating method. As a result, voids are formed from the portions where Ti is exposed to the surface in the following Cu plating film formation. With future miniaturization, Cu has to be buried at a high aspect ratio upon the formation of a Cu film and it is difficult to avoid the present situation. Therefore, immediate countermeasures are desired.